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s6b 07 28 132 seg / 1 28 com driver & controller for stn lcd jan . 2000 . ver. 0. 1 prepared by: goohyung, chung k uku81 @samsung.co.kr S6B0728 specification revision history contents in this document are subject to change without notice. no part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of lcd driver ic team.
132 seg / 128 com driver & controller for stn lcd preliminary spec. ver. 0. 1 S6B0728 2 version content date 0.0 original sep. 1999 0.1 change the supply voltage(vdd) range (2.4 to 5.5 -> 2.4 to 3.6) jan.2000
S6B0728 preliminary spec. ver. 0 . 1 132 seg / 1 28 com driver & controller for stn lcd 3 co ntents introduction ................................ ................................ ................................ ................................ .................. 1 block diagram ................................ ................................ ................................ ................................ ............... 2 pad configuration ................................ ................................ ................................ ................................ ....... 3 pad center coordinates ................................ ................................ ................................ ............................ 4 pin description ................................ ................................ ................................ ................................ .............. 6 functional description ................................ ................................ ................................ ............................ 10 microprocessor interface ................................ ................................ ................................ ............. 10 display data ram (ddram) ................................ ................................ ................................ .................. 14 lcd display circuits ................................ ................................ ................................ ............................ 17 lcd driver circuit ................................ ................................ ................................ ............................... 19 power supply circuits ................................ ................................ ................................ ...................... 21 reference circuit examples ................................ ................................ ................................ ........... 26 reset circuit ................................ ................................ ................................ ................................ ......... 28 instruction description ................................ ................................ ................................ ........................... 29 specifications ................................ ................................ ................................ ................................ .............. 48 absolute maximum ratings ................................ ................................ ................................ ............... 48 dc characteristics ................................ ................................ ................................ ............................. 49 ac characteristics ................................ ................................ ................................ ............................. 52 reference applications ................................ ................................ ................................ ........................... 56 microprocessor interface ................................ ................................ ................................ ............. 56 connections between S6B0728 and lcd panel ................................ ................................ ............ 57
S6B0728 preliminary spec. ver. 0 . 1 132 seg / 1 28 com driver & controller for stn lcd 1 introduction the S6B0728 is a driver and controller lsi for graphic dot-matrix liquid crystal display systems. it contains 1 28 common and 1 32 segment driver circuits. it is connected directly to a microprocessor, accepts serial or 8-bit parallel display data and stores in an on-chip display data ram of 128 x 1 32 bits. it provides a highly flexible display section due to 1-to-1 correspondence between on-chip display data ram bits and lcd panel pixels. and it performs display data ram read/write operation with no external-operating clock to minimize power consumption. in addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components. features driver output circuits - 1 28 common outputs / 1 32 segment outputs applicable duty-ratios programmable duty ratio applicable lcd bias maximum display area 1/ 16 to 1/1 28 1/ 5 to 1/1 2 1 28 1 32 - various partial display - partial window moving & data scrolling on-chip display data ram - capacity: 128 x 1 32 = 16,896 bits - bit data "1": a dot of display is illuminated - bit data "0": a dot of display is not illuminated microprocessor interface - 8-bit parallel bi-directional interface with 6800-series or 8080-series - serial interface(only write operation) with 4-pin or 3-pin spi(serial peripheral interface) on-chip low power analog circuit - on-chip oscillator circuit - voltage converter (x3, x4, x5 , x 6 or x 7 ) - voltage regulator (temperature coefficient: -0.05%/ c or external input) - on-chip electronic contrast control function (64 steps) - voltage follower (lcd bias: 1/ 5 to 1/1 2 ) operating voltage range - supply voltage (v dd ): 2.4 to 3.6 [ v ] - lcd driving voltage (v lcd = v0 - v ss ): 4.0 to 17.0 [ v ] low power consumption - tbd m a typ. (v dd = 3v, x 6 boosting, v0 = 1 5 v, internal power supply on and display off) - tbd m a max. (during power save [standby] mode ) package type - gold bumped chip or tcp
132 seg / 128 com driver & controller for stn lcd preliminary spec. ver. 0. 1 S6B0728 2 block diagram vdd v0 v1 v2 v3 v4 vss v0 vr intrs vext ref vout c1- c1+ c2- c2+ c3+ c4+ c5+ c6+ vci v/c circuit v / r rcircuit v/ f circuit 128 common driver circuits mpu interface (parallel & serial) instruction decoder & register status register bus holder column address circuit line address circuit page address circuit display data ram 128 x 1 32 = 16,896 bits segment controller timing generator circuit common controller db0 db1 db2 db3 db4 db5 db6(sclk) db7(sid) rw_wr e_rd rs cs2 cs1b ps c68 resetb com 127 com 126 : : : com 1 com 0 seg 131 seg 130 seg 129 : : seg2 seg1 seg0 oscillator 1 32 segment driver circuits figure 1 . block diagram
S6B0728 preliminary spec. ver. 0 . 1 132 seg / 1 28 com driver & controller for stn lcd 3 pad configuration ee eeeeeeeeeeeeeeeeeee - - - - - - - - - - eeeeeeeeeeeeeeeeeee ee y 16 1 3 12 16 0 3 13 127 3 46 1 2 6 1 s6b 07 28 (top view) (0,0) x eeeeeeeeeeeeeeeeeeeeee - - - - - - - - - - eeeeeeeeeeeeeeeeeeeeeee eeee - - - - eeee eeee - - - - eeee *2 *1 *3 figure 2 . S6B0728 chip configuration table 1 . S6B0728 pad dimensions size item pad no. x y unit chip size - 8740 2470 27 to 100 70 (m in. ) pad pitch 1 to 26, 101 to 346 54 (m in. ) 27 to 100 60 78 128 to 159, 314 to 345 78 44 3 to 26, 101 to 124 163 to 310 44 78 1, 2, 125, 126, 160, 161, 313, 346 70 78 bumped pad size 127, 162, 311, 312 78 70 bumped pad height 1 to 346 14 (typ.) m m 30 um 30 um 30 um 30 um 30 um 30 um (-3810, -705) *1 : bump align key 42 um 108 um 42 um (-3920, 825) 108 um *2 : ilb align key 1 42 um 108 um 42 um (3870, 783) 108 um *3 : ilb align key 2
132 seg / 128 com driver & controller for stn lcd preliminary spec. ver. 0. 1 S6B0728 4 pad center coordinates table 2 . pad center coordinates [unit: m m] no name x y no name x y no name x y no name x y 1 dummy -4161 -1110 51 db6 -875 -1110 101 com63 2759 -1110 151 com16 4245 405 2 dummy -4081 -1110 52 db7 -805 -1110 102 com62 2813 -1110 152 com15 4245 459 3 com104 -4001 -1110 53 vdd -735 -1110 103 com61 2867 -1110 153 com14 4245 513 4 com105 -3947 -1110 54 vdd -665 -1110 104 com60 2921 -1110 154 com13 4245 567 5 com106 -3893 -1110 55 vdd -595 -1110 105 com59 2975 -1110 155 com12 4245 621 6 com107 -3839 -1110 56 vdd -525 -1110 106 com58 3029 -1110 156 com11 4245 675 7 com108 -3785 -1110 57 vci -455 -1110 107 com57 3083 -1110 157 com10 4245 729 8 com109 -3731 -1110 58 vci -385 -1110 108 com56 3137 -1110 158 com9 4245 783 9 com110 -3677 -1110 59 vss -315 -1110 109 com55 3191 -1110 159 com8 4245 837 10 com111 -3623 -1110 60 vss -245 -1110 110 com54 3245 -1110 160 dummy 4245 917 11 com112 -3569 -1110 61 vss -175 -1110 111 com53 3299 -1110 161 dummy 4129 1110 12 com113 -3515 -1110 62 vss -105 -1110 112 com52 3353 -1110 162 dummy 4049 1110 13 com114 -3461 -1110 63 vout -35 -1110 113 com51 3407 -1110 163 com7 3969 1110 14 com115 -3407 -1110 64 vout 35 -1110 114 com50 3461 -1110 164 com6 3915 1110 15 com116 -3353 -1110 65 c5+ 105 -1110 115 com49 3515 -1110 165 com5 3861 1110 16 com117 -3299 -1110 66 c5+ 175 -1110 116 com48 3569 -1110 166 com4 3807 1110 17 com118 -3245 -1110 67 c3+ 245 -1110 117 com47 3623 -1110 167 com3 3753 1110 18 com119 -3191 -1110 68 c3+ 315 -1110 118 com46 3677 -1110 168 com2 3699 1110 19 com120 -3137 -1110 69 c1- 385 -1110 119 com45 3731 -1110 169 com1 3645 1110 20 com121 -3083 -1110 70 c1- 455 -1110 120 com44 3785 -1110 170 com0 3591 1110 21 com122 -3029 -1110 71 c1+ 525 -1110 121 com43 3839 -1110 171 seg0 3537 1110 22 com123 -2975 -1110 72 c1+ 595 -1110 122 com42 3893 -1110 172 seg1 3483 1110 23 com124 -2921 -1110 73 c2+ 665 -1110 123 com41 3947 -1110 173 seg2 3429 1110 24 com125 -2867 -1110 74 c2+ 735 -1110 124 com40 4001 -1110 174 seg3 3375 1110 25 com126 -2813 -1110 75 c2- 805 -1110 125 dummy 4081 -1110 175 seg4 3321 1110 26 com127 -2759 -1110 76 c2- 875 -1110 126 dummy 4161 -1110 176 seg5 3267 1110 27 test1 -2555 -1110 77 c4+ 945 -1110 127 dummy 4245 -917 177 seg6 3213 1110 28 test2 -2485 -1110 78 c4+ 1015 -1110 128 com39 4245 -837 178 seg7 3159 1110 29 test3 -2415 -1110 79 c6+ 1085 -1110 129 com38 4245 -783 179 seg8 3105 1110 30 cl -2345 -1110 80 c6+ 1155 -1110 130 com37 4245 -729 180 seg9 3051 1110 31 m -2275 -1110 81 vss 1225 -1110 131 com36 4245 -675 181 seg10 2997 1110 32 vdd -2205 -1110 82 vss 1295 -1110 132 com35 4245 -621 182 seg11 2943 1110 33 ps -2135 -1110 83 v4 1365 -1110 133 com34 4245 -567 183 seg12 2889 1110 34 c68 -2065 -1110 84 v4 1435 -1110 134 com33 4245 -513 184 seg13 2835 1110 35 vss -1995 -1110 85 v3 1505 -1110 135 com32 4245 -459 185 seg14 2781 1110 36 cs1b -1925 -1110 86 v3 1575 -1110 136 com31 4245 -405 186 seg15 2727 1110 37 cs2 -1855 -1110 87 v2 1645 -1110 137 com30 4245 -351 187 seg16 2673 1110 38 vdd -1785 -1110 88 v2 1715 -1110 138 com29 4245 -297 188 seg17 2619 1110 39 resetb -1715 -1110 89 v1 1785 -1110 139 com28 4245 -243 189 seg18 2565 1110 40 rs -1645 -1110 90 v1 1855 -1110 140 com27 4245 -189 190 seg19 2511 1110 41 vss -1575 -1110 91 v0 1925 -1110 141 com26 4245 -135 191 seg20 2457 1110 42 rw_wr -1505 -1110 92 v0 1995 -1110 142 com25 4245 -81 192 seg21 2403 1110 43 e_rd -1435 -1110 93 vr 2065 -1110 143 com24 4245 -27 193 seg22 2349 1110 44 vdd -1365 -1110 94 vr 2135 -1110 144 com23 4245 27 194 seg23 2295 1110 45 db0 -1295 -1110 95 vss 2205 -1110 145 com22 4245 81 195 seg24 2241 1110 46 db1 -1225 -1110 96 ref 2275 -1110 146 com21 4245 135 196 seg25 2187 1110 47 db2 -1155 -1110 97 vext 2345 -1110 147 com20 4245 189 197 seg26 2133 1110 48 db3 -1085 -1110 98 vdd 2415 -1110 148 com19 4245 243 198 seg27 2079 1110 49 db4 -1015 -1110 99 intrs 2485 -1110 149 com18 4245 297 199 seg28 2025 1110 50 db5 -945 -1110 100 vss 2555 -1110 150 com17 4245 351 200 seg29 1971 1110
S6B0728 preliminary spec. ver. 0 . 1 132 seg / 1 28 com driver & controller for stn lcd 5 table 2 . pad center coordinates (continued) [unit: m m] no name x y no name x y no name x y 201 seg30 1917 1110 251 seg80 -783 1110 301 seg130 -3483 1110 202 seg31 1863 1110 252 seg81 -837 1110 302 seg131 -3537 1110 203 seg32 1809 1110 253 seg82 -891 1110 303 com64 -3591 1110 204 seg33 1755 1110 254 seg83 -945 1110 304 com65 -3645 1110 205 seg34 1701 1110 255 seg84 -999 1110 305 com66 -3699 1110 206 seg35 1647 1110 256 seg85 -1053 1110 306 com67 -3753 1110 207 seg36 1593 1110 257 seg86 -1107 1110 307 com68 -3807 1110 208 seg37 1539 1110 258 seg87 -1161 1110 308 com69 -3861 1110 209 seg38 1485 1110 259 seg88 -1215 1110 309 com70 -3915 1110 210 seg39 1431 1110 260 seg89 -1269 1110 310 com71 -3969 1110 211 seg40 1377 1110 261 seg90 -1323 1110 311 dummy -4049 1110 212 seg41 1323 1110 262 seg91 -1377 1110 312 dummy -4129 1110 213 seg42 1269 1110 263 seg92 -1431 1110 313 dummy -4245 917 214 seg43 1215 1110 264 seg93 -1485 1110 314 com72 -4245 837 215 seg44 1161 1110 265 seg94 -1539 1110 315 com73 -4245 783 216 seg45 1107 1110 266 seg95 -1593 1110 316 com74 -4245 729 217 seg46 1053 1110 267 seg96 -1647 1110 317 com75 -4245 675 218 seg47 999 1110 268 seg97 -1701 1110 318 com76 -4245 621 219 seg48 945 1110 269 seg98 -1755 1110 319 com77 -4245 567 220 seg49 891 1110 270 seg99 -1809 1110 320 com78 -4245 513 221 seg50 837 1110 271 seg100 -1863 1110 321 com79 -4245 459 222 seg51 783 1110 272 seg101 -1917 1110 322 com80 -4245 405 223 seg52 729 1110 273 seg102 -1971 1110 323 com81 -4245 351 224 seg53 675 1110 274 seg103 -2025 1110 324 com82 -4245 297 225 seg54 621 1110 275 seg104 -2079 1110 325 com83 -4245 243 226 seg55 567 1110 276 seg105 -2133 1110 326 com84 -4245 189 227 seg56 513 1110 277 seg106 -2187 1110 327 com85 -4245 135 228 seg57 459 1110 278 seg107 -2241 1110 328 com86 -4245 81 229 seg58 405 1110 279 seg108 -2295 1110 329 com87 -4245 27 230 seg59 351 1110 280 seg109 -2349 1110 330 com88 -4245 -27 231 seg60 297 1110 281 seg110 -2403 1110 331 com89 -4245 -81 232 seg61 243 1110 282 seg111 -2457 1110 332 com90 -4245 -135 233 seg62 189 1110 283 seg112 -2511 1110 333 com91 -4245 -189 234 seg63 135 1110 284 seg113 -2565 1110 334 com92 -4245 -243 235 seg64 81 1110 285 seg114 -2619 1110 335 com93 -4245 -297 236 seg65 27 1110 286 seg115 -2673 1110 336 com94 -4245 -351 237 seg66 -27 1110 287 seg116 -2727 1110 337 com95 -4245 -405 238 seg67 -81 1110 288 seg117 -2781 1110 338 com96 -4245 -459 239 seg68 -135 1110 289 seg118 -2835 1110 339 com97 -4245 -513 240 seg69 -189 1110 290 seg119 -2889 1110 340 com98 -4245 -567 241 seg70 -243 1110 291 seg120 -2943 1110 341 com99 -4245 -621 242 seg71 -297 1110 292 seg121 -2997 1110 342 com100 -4245 -675 243 seg72 -351 1110 293 seg122 -3051 1110 343 com101 -4245 -729 244 seg73 -405 1110 294 seg123 -3105 1110 344 com102 -4245 -783 245 seg74 -459 1110 295 seg124 -3159 1110 345 com103 -4245 -837 246 seg75 -513 1110 296 seg125 -3213 1110 346 dummy -4245 -917 247 seg76 -567 1110 297 seg126 -3267 1110 248 seg77 -621 1110 298 seg127 -3321 1110 249 seg78 -675 1110 299 seg128 -3375 1110 250 seg79 -729 1110 300 seg129 -3429 1110
132 seg / 128 com driver & controller for stn lcd preliminary spec. ver. 0. 1 S6B0728 6 pin description table 3 . power s upply p ins name i/o description v dd supply power supply vss supply ground lcd drivers supply voltages the voltage determined by lcd pixel is impedance-converted by an operational amplifier for application. voltages should have the following relationship: v0 3 v1 3 v2 3 v3 3 v4 3 vss when the internal power circuit is active, these voltages are generated as following table according to the state of lcd b ias. lcd bias v1 v2 v3 v4 1/n bias (n-1)/n x v0 (n-2)/n x v0 2/n x v0 1/n x v0 v0 v1 v2 v3 v4 i/o note : *n = 5 to 1 2 table 4 . lcd driver supply p ins name i/o description c1- , c2- i/ o capacitor negative connection pin s used for voltage converter c1+ , c2+ c3+ , c4+ c5+ , c 6 + i/ o capacitor positive connection pin s used for voltage converter vout i/o voltage converter input/output pin . vout = boost level vci, for internal booster vci i voltage converter input voltage pin for internal booster. vr i v0 voltage adjustment pin used to adjust v0 by means of external resistors( intrs = ? l ? ) ref i selects the external vref voltage via vext pin - ref = "l": using the external vref - ref = "h": using the internal vref vext i externally - input reference voltage(vref) for the internal voltage regulator. it is valid only when ref is ? l ? . intrs i internal resistors select pin used to select r esistors for adjusting v0 voltage level. - intrs = "h ? : use the internal resistors. - intrs = "l ? : use the external resistors. vr pin and external resistive divider control v0 voltage .
S6B0728 preliminary spec. ver. 0 . 1 132 seg / 1 28 com driver & controller for stn lcd 7 table 5 . microprocessor interface p ins name i/o description resetb i reset input pin . when resetb is ? l ? , initialization is executed. parallel / serial data input select input ps interface mode data / instruction data read / write serial clock h parallel rs db0 to db7 e_rd rw_wr - l serial rs sid (db7) write only sclk (db6) ps i *note: when ps is ? l ? , db0 to db5 are high impedance and e_rd and rw_wr must be fixed to either ? h ? or ? l ? . microprocessor interface (ps = ? h ? ) / register select(ps = ? l ? ) input pin ps c68 interface mode h 6800-series mpu mode h l 8080-series mpu mode h 4-pin spi mpu mode l l 3-pin spi mpu mode c68 i cs1b cs2 i chip select input pins data / instruction i/o is enabled only when cs1b is ? l ? and cs2 is ? h ? . when chip select is non-active, db0 to db7 may be high impedance. rs i register select input pin - rs = "h": db0 to db7 are display dat a - rs = "l": db0 to db7 are control data read / write execution control pin c68 mpu type rw_wr description h 6800-series rw read/write control input pin - rw = ? h ? : read - rw = ? l ? : write l 8080-series /wr write enable clock input pin the data on db0 to db7 are latched at the rising edge of the /wr signal. rw_wr i
132 seg / 128 com driver & controller for stn lcd preliminary spec. ver. 0. 1 S6B0728 8 table 5 . microprocessor interface p ins (continued) name i/o description read / write execution control pin c68 mpu t ype e_rd description h 6800-series e read / write control input pin - rw = ? h ? : when e is ? h ? , db0 to db7 are in an output status. - rw = ? l ? : the data on db0 to db7 are latched at the falling edge of the e signal. l 8080-series /rd read enable clock input pin when /rd is ? l ? , db0 to db7 are in an output status. e_rd i db0 to db7 i/o 8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data bus. when the serial interface selected (ps = "l"); - db0 to db5: high impedance - db6: serial input clock (sclk) - db7: serial input data (sid). when chip select is not active, db0 to db7 may be high impedance. table 6 . test p ins name i/o description test1 to test 3 i test pins don ? t use these pins.
S6B0728 preliminary spec. ver. 0 . 1 132 seg / 1 28 com driver & controller for stn lcd 9 table 7 . lcd driver output pins name i/o description lcd segment driver outputs the display data and the m signal control the output voltage of segment driver. segment driver output voltage display data m normal display reverse display h h v0 v2 h l vss v3 l h v2 v0 l l v3 vss power save mode vss vss seg0 to seg 131 o lcd common driver outputs the internal scanning data and m signal control the output voltage of common driver. scan data m common driver output voltage h h vss h l v0 l h v1 l l v4 power save mode vss com0 to com 127 o
132 seg / 128 com driver & controller for stn lcd preliminary spec. ver. 0. 1 S6B0728 10 functional description microprocessor interface chip select input there are cs1b and cs2 pins for c hip s election. the S6B0728 can interface with an mpu only when cs1b is ? l ? and cs2 is ? h ? . when these pins are set to any other combination, rs, e_rd, and rw_wr inputs are disabled and db0 to db7 are to be high impedance. and, in case of serial interface, the internal shift register and the counter are reset. parallel / serial interface the S6B0728 has four types of interface with an mpu, which are two serial and two parallel interfaces. this parallel or serial interface is determined by ps pin as shown in table 8 . table 8 . parallel / serial interface mode. ps type cs1b cs2 c68 interface mode h 6800-series mpu mode h parallel cs1b cs2 l 8080-series mpu mode h 4-pin spi mpu mode l serial cs1b cs2 l 3-pin spi mpu mode parallel interface (ps = "h") the 8-bit bi-directional data bus is used in parallel interface and the type of mpu is selected by c68 as shown in table 9 . the type of data transfer is determined by signals at rs, e_rd and rw_wr as shown in table 10 . table 9 . microprocessor selection for parallel interface c68 cs1b cs2 rs e_rd rw_wr db0 to db7 mpu bus h cs1b cs2 rs e rw db0 to db7 6800-series l cs1b cs2 rs /rd /wr db0 to db7 8080-series table 10 . parallel data transfer common 6800-series 8080-series rs e_rd (e) rw_wr (rw) e_rd (/rd) rw_wr (/wr) description h h h l h read d isplay data h h l h l write d isplay data l h h l h read out internal status r egister l h l h l write instruction data
S6B0728 preliminary spec. ver. 0 . 1 132 seg / 1 28 com driver & controller for stn lcd 11 serial interface (ps = "l") communication with the microprocessor occurs via a clock-synchronized serial peripheral interface when ps is low. when using the serial interface, read operations are not allowed. . when the chip select inputs are valid(cs1b = ? l ? & cs2 = ? h ? ) , the s erial data is sent most significant bit first on the rising edge of a serial clock going into db6 and processed as 8-bit parallel data on the eighth clock . since the clock signal is easy to be affected by the external noise caused by the line length, the operation check on the actual machine is recommended . and not valid , the internal 8-bit shift register and the 3-bit counter are reset. t he serial interface type is selected by setting c68 as shown in table 11 . table 11 . microprocessor selection for serial interface c68 serial interface mode chip select register select serial data / clock input h 4-pin spi cs1b , cs2 by rs pin db7 / db6 l 3-pin spi cs1b , cs2 by software db7 / db6 4-pin spi interface (ps = "l" , c68 = " h ") in 4-pin spi interface mode, rs pin is used for indicating whether serial data input is display or instruction data. d ata is display data when rs is high and instruction data when rs is low. cs1b cs2 sid sclk rs db6 db7 db0 db1 db2 db3 db4 db5 db6 db7 figure 3 . 4-pin spi timing (rs is used)
132 seg / 128 com driver & controller for stn lcd preliminary spec. ver. 0. 1 S6B0728 12 3-pin spi interface (ps = "l" , c68 = " l ") in 3-pin spi interface mode, the pre-defined instruction called display data length, is used to indicate whether serial data input is display or instruction data instead of rs pin. the data is handled as instruction data until the display data length instruction is issued. this display data length instruction consists two bytes instruction. the first byte instruction enables the next instruction to be valid, and the data of the second byte indicates that a specified number of display data bytes(1 to 256) are to be transmitted. the next byte after the display data string is handled as instruction data. for details, refers the figure 4 . chip select serial clock cs1b = l, cs2 = h 24 1 23 2 1 16 serial data 10110001 00010000 00001000 11111100 00001001 2 15 1 2 80 79 internal rs 10 bytes display data page = 1 column address = 16 ddl ddl = 9 user's display data 3 bytes 10 bytes 2 bytes figure 4 . 3 pin spi timing (rs is not used) *notes: - in spite of transmission of d ata, if cs1b will be disable, state terminates abnormally. next state is initialized. - the number of writing display data = ddl register value + 1 busy flag the b usy f lag indicates whether the S6B0728 is operating or not. when db7 is ? h ? in read status operation, this device is in busy status and will accept only read status instruction. if the cycle time is correct, the microprocessor needs not to check this flag before each instruction, which improves the mpu performance.
S6B0728 preliminary spec. ver. 0 . 1 132 seg / 1 28 com driver & controller for stn lcd 13 data transfer the S6B0728 uses bus holder and internal data bus for data transfer with the mpu. when writing data from the mpu to on-chip ram, data is automatically transferred from the bus holder to the ram as shown in figure 4. and when reading data from on-chip ram to the mpu, the data for the initial read cycle is stored in the bus holder (dummy read) and the mpu reads this stored data from bus holder for the next data read cycle as shown in figure 5. this means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. t herefore, the data of the specified address cannot be output with the r ead d isplay d ata instruction right after the address sets, but can be output at the second read of data. rs /wr db0 to db7 n d(n) d(n+1) d(n+2) d(n+3) internal signals mpu signals /wr bus holder column address n n+1 n+2 n+3 n d(n) d(n+1) d(n+2) d(n+3) figure 5 . write timing rs /wr /rd db0 to db7 n mpu signals dummy d(n) d(n+1) internal signals /wr /rd bus holder column address n d(n) d(n+1) d(n+2) n n+1 n+2 n+3 figure 6 . read timing
132 seg / 128 com driver & controller for stn lcd preliminary spec. ver. 0. 1 S6B0728 14 display data ram (ddram) the display data ram stores pixel data for the lcd. it is 128 -row by 1 32 -column addressable array. each pixel can be selected when the page and column addresses are specified. the 128 rows are divided into 1 6 pages of 8 lines. data is read from or written to the 8 lines of each page directly through db0 to db7. the display data of db0 to db7 from the microprocessor correspond to the lcd common lines as shown in figure 6 . the microprocessor can read from and write to ram through the i/o buffer. since the lcd controller operates independently, data can be written into ram at the same time as data is being displayed without causing the lcd flicker. com0 - - com1 - - com2 - - com3 - - com4 - - db0 0 0 1 - - 0 db1 1 0 0 - - 1 db2 0 1 1 - - 0 db3 1 0 1 - - 0 db4 0 0 0 - - 1 d isplay d ata ram lcd display figure 7 . ram-to-lcd data transfer page address circuit this circuit is for providing a p age a ddress to display data ram shown in f igure 8 . it incorporates 4-bit p age a ddress register changed by only the ? set page ? instruction. line address circuit this circuit assigns ddram a line address corresponding to the first line (com0) of the display. therefore, by setting line address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on-chip ram as shown in figure 7. it incorporates 7-bit line address register changed by only the i nitial d isplay l ine instruction and 7-bit counter circuit. at the beginning of each lcd frame, the contents of register are copied to the line counter which is increased by internal latch signal and generates the l ine a ddress for transferring the 1 32 -bit ram data to the display data latch circuit. however, display data of icons are not scrolled because the mpu can not access l ine a ddress of icons.
S6B0728 preliminary spec. ver. 0 . 1 132 seg / 1 28 com driver & controller for stn lcd 15 column address circuit column a ddress circuit has an 8 -bit preset counter that provides c olumn a ddress to the display data ram as shown in figure 8 . when set column address msb / lsb instruction is issued, 8 -bit [y 7 :y0] is updated. and, since this address is increased by 1 each a read or write data instruction, microprocessor can access the display data continuously. however, the counter is not incremented and locked if a non-existing address above 83 h. it is unlocked if a column address is set again by s et column address msb / lsb instruction. and t he c olumn a ddress counter is independent of page address register. adc s elect instruction makes it possible to invert the relationship between the c olumn a ddress and the segment outputs. it is necessary to rewrite the display data on built-in ram after issuing adc s elect instruction. r efer to the following figure 7 . seg output seg 0 seg 1 seg 2 seg 3 ... ... seg 128 seg 129 seg 130 seg 131 column a ddress [y 7 :y0] 00h 01h 02h 03h ... ... 80 h 81 h 82 h 83 h display data 1 0 1 0 1 1 0 0 lcd panel d isplay ( adc = 0 ) ... ... lcd p anel d isplay ( adc = 1 ) ... ... figure 8 . the relationship between the column address and the segment outputs segment control circuit this circuit controls the display data by the display on / off, reverse d isplay o n / o ff and e ntire d isplay on / off instructions without changing the data in the display data ram.
132 seg / 128 com driver & controller for stn lcd preliminary spec. ver. 0. 1 S6B0728 16 line address com output page address db3 db0 db1 db2 data initial start line address = 08h page 0 0 0 0 0 db0 db1 db2 db3 db4 db5 db6 db7 00h 01h 02h 03h 04h 05h 06h 07h page 1 0 1 0 0 db0 db1 db2 db3 db4 db5 db6 db7 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh page 2 0 0 1 0 db0 db1 db2 db3 db4 db5 db6 db7 page 3 0 1 1 0 db0 db1 db2 db3 db4 db5 db6 db7 page 12 1 0 0 1 db0 db1 db2 db3 db4 db5 db6 db7 page 13 1 1 0 1 db0 db1 db2 db3 db4 db5 db6 db7 page 14 1 0 1 1 db0 db1 db2 db3 db4 db5 db6 db7 page 15 1 1 1 1 db0 db1 db2 db3 db4 db5 db6 db7 com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com96 com97 com98 com99 com100 com101 com102 com103 com104 com105 com106 com107 com108 com109 com110 com111 com112 com113 com114 com115 com116 com117 com118 com119 com120 com121 com122 com123 com124 com125 com126 com127 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 68h 69h 6ah 6bh 6ch 6dh 6eh 6fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7ah 7bh 7ch 7dh 7eh 7fh 60h 61h 62h 63h 64h 65h 66h 67h 1/128 duty 1/104 duty start = 08h end = 07h 02 03 01 04 05 - - - - - - - - 80 81 7e 7f 82 83 02 03 00 01 04 05 - - - - - - - - 80 81 7e 7f 82 83 adc=0 adc=1 column address 00 lcd segment output - - - - - - - - seg0 seg1 seg2 seg3 seg4 seg5 seg126 seg127 seg128 seg129 seg130 seg131 figure 9 . display data ram map
S6B0728 preliminary spec. ver. 0 . 1 132 seg / 1 28 com driver & controller for stn lcd 17 lcd display circuits oscillator this is completely on-chip o scillator and its frequency is nearly independent of v dd . this oscillator signal is used in the voltage converter and display timing generation circuit. display timing generator circuit this circuit generates some signals to be used for displaying lcd. the internal display clock, cl, generated by oscillation clock, generates the clock for the line counter and the signal for the display data latch. the line address of on-chip ram is generated in synchronization with the display clock (cl) and the display data latch circuit in synchronization latches the 1 32 -bit display data with the display clock. the display data, which is read to the lcd driver, is completely independent of the access to the display data ram from the microprocessor. the display clock generates an lcd ac signal (m) which enables the lcd driver to make a ac drive waveform, and also generates an internal common timing signal and start signal to the common driver. the frame or the line changes the phase of m by setting internal instruction. driving waveform and internal timing signal are shown in figure 10.
132 seg / 128 com driver & controller for stn lcd preliminary spec. ver. 0. 1 S6B0728 18 fr m 84 85 1 2 3 4 5 6 7 8 9 10 11 12 78 79 80 81 82 83 84 85 1 2 3 4 5 6 cl com0 v0 v1 v2 v3 v4 vss com1 v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss segn figure 10 . 2-frame ac driving waveform (duty ratio = 1/ 8 5) fr m 84 85 1 2 3 4 5 6 7 8 9 10 11 12 78 79 80 81 82 83 84 85 1 2 3 4 5 6 cl com0 v0 v1 v2 v3 v4 vss com1 v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss segn figure 11 . n-line inversion driving waveform (n = 5, duty ratio = 1/ 8 5)
S6B0728 preliminary spec. ver. 0 . 1 132 seg / 1 28 com driver & controller for stn lcd 19 lcd driver circuit 1 28 -channel common driver and 1 32 -channel segment driver configure this driver circuit. this lcd panel driver voltage depends on the combination of display data and m signal. com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 s e g 4 s e g 3 s e g 2 s e g 1 s e g 0 seg2 seg1 seg0 com2 com0 com1 m v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss vdd vss figure 12 . segment and common timing
132 seg / 128 com driver & controller for stn lcd preliminary spec. ver. 0. 1 S6B0728 20 partial display on lcd the S6B0728 realizes the partial display function on lcd with low-duty driving for saving power consumption and showing the various display duties. to show the various display duties on lcd, lcd driving duty and bias are programmable via the instruction. and, built-in power supply circuits are controlled by the instruction for adjusting the lcd driving voltages -- com0 -- com1 -- com2 -- com3 -- com4 -- com5 -- com6 -- com7 -- com8 -- com9 -- com10 -- com11 -- com12 -- com13 -- com14 -- com15 -- com16 -- com17 -- com18 -- com19 -- com20 -- com21 -- com22 -- com23 reference example for partial display ( display duty = 24 ) -- com0 -- com1 -- com2 -- com3 -- com4 -- com5 -- com6 -- com7 -- com8 -- com9 -- com10 -- com11 -- com12 -- com13 -- com14 -- com15 -- com16 -- com17 -- com18 -- com19 -- com20 -- com21 -- com22 -- com23 partial display ( partial display duty = 8, initial com0 = 0 ) -- com0 -- com1 -- com2 -- com3 -- com4 -- com5 -- com6 -- com7 -- com8 -- com9 -- com10 -- com11 -- com12 -- com13 -- com14 -- com15 -- com16 -- com17 -- com18 -- com19 -- com20 -- com21 -- com22 -- com23 moving display ( partial display duty = 8, initial com0 = 8 ) figure 13 . reference example for partial display
S6B0728 preliminary spec. ver. 0 . 1 132 seg / 1 28 com driver & controller for stn lcd 21 power supply circuits the p ower s upply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low- power consumption and the fewest components. there are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. they are valid only in master operation and controlled by p ower c ontrol instruction. for details, refers to "instruction description". table 12 shows the referenced combinations in using p ower s upply circuits. table 12 . recommended power supply combinations user setup power control (vc vr vf) v/c circuits v/r circuits v/f circuits vout v0 v1 to v4 only the internal power supply circuits are used 1 1 1 on on on open open open only the voltage regulator circuits and voltage follower circuits are used 0 1 1 off on on external input open open only the voltage follower circuits are used 0 0 1 off off on external input open open only the external power supply circuits are used 0 0 0 off off off open external input external input
132 seg / 128 com driver & controller for stn lcd preliminary spec. ver. 0. 1 S6B0728 22 voltage converter circuits these circuits boost up the electric potential between vci and vss to 3, 4, 5 , 6 or 7 times toward positive side and boosted voltage is outputted from vout pin. it is possible to select the lower boosting level in any boosting circuit by ? set dc-dc step-up ? instruction. when the higher level is selected by instruction, vout voltage is not valid. [c1 = 1.0 to 4.7 m f] vout = boost level x vci vss vout c5+ c3+ c1- c1+ c2+ c2- c4+ c6+ + - + - + - + - + - + - x6 vss vout c5+ c3+ c1- c1+ c2+ c2- c4+ c6+ + - + - + - + - + - + - + - x7 vss vout c5+ c3+ c1- c1+ c2+ c2- c4+ c6+ + - + - + - + - + - x5 vss vout c5+ c3+ c1- c1+ c2+ c2- c4+ c6+ + - + - + - + - x4 vss vout c5+ c3+ c1- c1+ c2+ c2- c4+ c6+ + - + - + - x3 figure 14 . boosting circuit s
S6B0728 preliminary spec. ver. 0 . 1 132 seg / 1 28 com driver & controller for stn lcd 23 voltage regulator circuits the function of the internal voltage regulator circuits is to determine liquid crystal operating voltage, v0, by adjusting resistors, ra and rb, within the range of |v0| < |vout|. because vout is the operating voltage of operational-amplifier circuits shown in figure 19 , it is necessary to be applied internally or externally. for the eq. 6-1, we determine v0 by ra, rb and v ev . the ra and rb are connected internally or externally by intrs pin. and v ev called the voltage of electronic volume is determined by eq. 6-2, where the parameter a is the value selected by instruction, "set reference voltage register", within the range 0 to 63. v ref voltage at ta = 25 c is shown in table 13 . v0 = (1 + ( rb / ra ) ) x v ev [v] ------ (eq. 6-1) v ev = (1 ? ( ( 63 - a ) / 200 ) ) x v ref [v] ------ (eq. 6-2) table 13 . v ref voltage at ta = 25 c ref temp. coefficient v ref [v] 1 -0.05% / c 2.0 0 external input vext v ev gnd ra rb vss vr v0 vout + - figure 15 . internal voltage regulator circuit
132 seg / 128 com driver & controller for stn lcd preliminary spec. ver. 0. 1 S6B0728 24 in case of using internal resistors, ra and rb (intrs = "h ? ) when intrs pin is ? h ? , resistor ra is connected internally between vr pin and v ss , and rb is connected between v0 and vr. we determine v0 by two instructions, "regulator resistor select" and "set reference voltage". 3-bit data settings (r2 r1 r0) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 + (rb / ra) 2.6 3.4 4.2 5.0 5.8 6.6 7.4 8.3 table 14 . internal rb / ra ratio depending on 3-bit data (r2 r1 r0) figure 16 shows v0 voltage measured by adjusting internal regulator register ratio (rb / ra) and 6-bit electronic volume registers for each temperature coefficient at ta = 25 c. 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 16.00 0 8 16 24 32 40 48 56 (1, 1, 1) (1, 1, 0) (1, 0, 1) (1, 0, 0) (0, 1, 1) (0, 1, 0) (0, 0, 1) (0, 0, 0) electr on ic volume register (0 to 63) v0 voltage [v] 63 figure 16 . v0 v oltage by 1 + (rb / ra) and electronic volume level s
S6B0728 preliminary spec. ver. 0 . 1 132 seg / 1 28 com driver & controller for stn lcd 25 in case of using external resistors, ra and rb (intrs = "l") when intrs pin is ? l ? , it is necessary to connect external regulator resistor ra between vr and vss, and rb between v0 and vr. example: for the following requirements 1. lcd driver voltage, v0 = 10v 2. 6-bit reference voltage register = (1 , 0, 0, 0, 0, 0) 3. maximum current flowing ra, rb = 1 u a from eq. 6.1 10 = (1 + ( rb / ra ) ) x v ev [v] ------ (eq. 6 .3 ) from eq. 6. 2 v ev = (1 ? ( ( 63 - 32 ) / 200 ) ) x 2.0 = 1.69 [v] ------ (eq. 6 .4 ) from requirement 3. 10 / ( ra + rb ) = 1 [ua] ------ (eq. 6.5) from equations eq. 6.3, 6.4 and 6.5 ra = 1.69 [m w ] , rb = 8.31 [m w ] table 15 shows the range of v0 depending on the above requirements. table 15 . the range of v0 electronic volume level 0 ....... 32 ....... 63 v0 8.10 ....... 10.00 ....... 11.83 voltage follower circuits vlcd voltage (v0) is resistively divided into four voltage levels (v1, v2, v3 and v4), and th e se output impedance are converted by the voltage follower for increasing drive capability. table 16 shows the relationship between v1 to v4 level and each duty ratio. table 16 . v1 to v4 l evel lcd bias v1 v2 v3 v4 remarks 1/n (n-1)/n x v0 (n-1)/n x v0 2/n x v0 1/n x v0 n = 5 to 1 2
132 seg / 128 com driver & controller for stn lcd preliminary spec. ver. 0. 1 S6B0728 26 reference circuit examples [c1 = 1.0 to 4.7 [ m f], c2 = 0.1 to 0.47 [ m f]] when using internal regulator resistors (intrs = "vdd") when not using internal regulator resistors (intrs = "vss") v ss c1 c1 c1 c1 c1 + + + + + vout c5+ vr v4 v3 v2 v1 v0 c4+ c2 - c2+ c1+ c1 - c3+ rb ra c2 c2 c2 c2 c2 c6+ c1 c1 v ss c1 c1 c1 c1 c1 + + + + + vout c5+ vr v4 v3 v2 v1 v0 c4+ c2 - c2+ c1+ c1 - c3+ c2 c2 c2 c2 c2 c6+ c1 c1 figure 17 . when using a ll lcd power circuits (7-times v/c: o n , v/r: o n , v/f: on ) when using internal regulator resistors (intrs = "vdd") v ss + + + + + vout c5+ vr v4 v3 v2 v1 v0 c4+ c2 - c2+ c1+ c1 - c3+ c2 c2 c2 c2 c2 c6+ external vout when not using internal regulator resistors (intrs = "vss") external vout v ss + + + + + vout c5+ vr v4 v3 v2 v1 v0 c4+ c2 - c2+ c1+ c1 - c3+ rb ra c2 c2 c2 c2 c2 c6+ figure 18 . when using s ome lcd power circuits (v/c: o ff , v/r: o n , v/f: o n )
S6B0728 preliminary spec. ver. 0 . 1 132 seg / 1 28 com driver & controller for stn lcd 27 v ss + + + + + vout c5+ vr v4 v3 v2 v1 v0 c4+ c2 - c2+ c1+ c1 - c3+ c2 c2 c2 c2 c2 c6+ external vout figure 19 . when using o nly voltage follower circuit (v/c: o ff , v/r: o ff , v/f: o n ) external v0 v1 v2 v3 v4 v ss vout c5+ vr v4 v3 v2 v1 v0 c4+ c2 - c2+ c1+ c1 - c3+ c6+ figure 20 . when not using a ll lcd power circuits (v/c: o ff , v/r: o ff , v/f: o ff )
132 seg / 128 com driver & controller for stn lcd preliminary spec. ver. 0. 1 S6B0728 28 reset circuit setting resetb to ? l ? or reset instruction can initialize internal function. when resetb becomes ? l ? , following procedure is occurred. page address: 0 column address: 0 modify-read: o ff display o n / o ff : o ff initial display line: 0 (first) initial com0 register: 0 (com0) partial display duty ratio: 1/1 28 reverse display o n / o ff : off (normal) n-line inversion register: 0 (disable) entire display o n / o ff : off (normal) power control register (vc, vr, vf) = (0, 0, 0) dc-dc step up: 3 times converter circuit = ( 0, 0, 0) regulator resistor select register: (r2, r1, r0) = (0, 0, 0) reference voltage control register: (ev5, ev4, ev3, ev2, ev1, ev0) = (1, 0, 0, 0, 0, 0) lcd bias ratio: 1/1 2 shl select: off (normal) adc select: off (normal) oscillator status: off power save mode: release when reset instruction is issued, following procedure is occurred. page address: 0 column address: 0 modify-read: o ff initial display line: 0 ( f irst) regulator resistor select register: (r2, r1, r0) = (0, 0, 0) reference voltage control register (ev5, ev4, ev3, ev2, ev1, ev0) = (1, 0, 0, 0, 0, 0) while resetb is ? l ? or reset instruction is executed, no instruction except read status could be accepted. reset status appears at db4. after db4 becomes ? l ? , any instruction can be accepted. resetb must be connected to the reset pin of the mpu, and initialize the mpu and this lsi at the same time. the initialization by resetb is essential before used.
S6B0728 preliminary spec. ver. 0 . 1 132 seg / 1 28 com driver & controller for stn lcd 29 instruction description table 17 . instruction table : don ? t care instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 description read display data 1 1 read data read data from ddram write display data 1 0 write data write data into ddram read status 0 1 busy adc on res 0 0 0 0 read the internal status set page address 0 0 1 0 1 1 p3 p2 p1 p0 set page address set column address msb 0 0 0 0 0 1 y7 y6 y5 y4 set column address msb set column address lsb 0 0 0 0 0 0 y3 y2 y1 y0 set column address lsb set modify-read 0 0 1 1 1 0 0 0 0 0 set modify-read mode reset modify-read 0 0 1 1 1 0 1 1 1 0 release modify-read mode display on / off 0 0 1 0 1 0 1 1 1 d d = 0: display off d = 1: display on 0 0 0 1 0 0 0 0 set initial display line register 0 0 s6 s5 s4 s3 s2 s1 s0 2-byte i nstruction to specify the initial display line to realize vertical scrolling 0 0 0 1 0 0 0 1 set initial com0 register 0 0 c6 c5 c4 c3 c2 c1 c0 2-byte in struction to specify the initial com0 to realize window scrolling 0 0 0 1 0 0 1 0 set partial display duty ratio 0 0 d7 d6 d5 d4 d3 d2 d1 d0 2-byte i nstruction to set partial display duty ratio 0 0 0 1 0 0 1 1 set n-line inversion 0 0 n4 n3 n2 n1 n0 2-byte i nstruction to set n-line inversion register release n-line inversion 0 0 1 1 1 0 0 1 0 0 release n-line inversion mode reverse display on / off 0 0 1 0 1 0 0 1 1 rev rev = 0: normal display rev = 1: reverse display entire display on / off 0 0 1 0 1 0 0 1 0 eon eon = 0: normal display eon = 1: entire display on power control 0 0 0 0 1 0 1 vc vr vf control power circuit operation select dc-dc step-up 0 0 0 1 1 0 0 dc2 dc1 dc0 select the step-up of the internal voltage converter select regulator resistor 0 0 0 0 1 0 0 r2 r1 r0 select internal resistance ratio of the regulator resistor 0 0 1 0 0 0 0 0 0 1 set electronic volume register 0 0 ev5 ev4 ev3 ev2 ev1 ev0 2-byte i nstruction to specify the electronic volume register select lcd bias 0 0 0 1 0 1 0 b2 b1 b0 select lcd bias shl select 0 0 1 1 0 0 shl com bi-directional selection shl = 0: normal direction shl = 1: reverse direction adc select 0 0 1 0 1 0 0 0 0 adc seg bi-directional selection adc = 0: normal direction adc = 1: reverse direction oscillator on start 0 0 1 0 1 0 1 0 1 1 start the built-in oscillator set power save mode 0 0 1 0 1 0 1 0 0 1 power save mode release power save mode 0 0 1 1 1 0 0 0 0 1 release power save mode set ddl register 0 0 0 1 1 1 0 0 0 0 set ddl register in 3-pin serial mode reset 0 0 1 1 1 0 0 0 1 0 initialize the internal functions nop 0 0 1 1 1 0 0 0 1 1 no operation test instruction 0 0 1 1 1 1 don't use this instruction.
132 seg / 128 com driver & controller for stn lcd preliminary spec. ver. 0. 1 S6B0728 30 read display data 8-bit data from d isplay d ata ram specified by the column address and page address can be read by this instruction. as the column address is incremented by 1 automatically after each this instruction, the microprocessor can continuously read data from the addressed page. a dummy read is required after loading an address into the column address register. display data cannot be read through the serial interface. rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 1 read data write display data 8-bit data of display data from the microprocessor can be written to the ram location specified by the column address and page address. the column address is incremented by 1 automatically so that the microprocessor can continuously write data to the addressed page. rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 0 write data d ata w rite s et c olumn a ddress s et p age a ddress o ptional s tatus c olumn = c olumn +1 n o y es d ata w rite c ontinue ? d ummy d ata r ead s et c olumn a ddress s et p age a ddress op tional s tatus c olumn = c olumn +1 n o y es d ata r ead c ontinue ? d ata r ead c olumn = c olumn +1 figure 21 . sequence for writing display data figure 22 . sequence for reading display data
S6B0728 preliminary spec. ver. 0 . 1 132 seg / 1 28 com driver & controller for stn lcd 31 read status indicates the internal status of the S6B0728 rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 1 busy adc on res 0 0 0 0 flag description busy the device is busy when internal operation or reset any instruction is rejected until busy goes low. 0: c hip is active, 1: c hip is being busy. adc indicates the relationship between ram column address and segment driver. 0: reverse direction (seg 131 ? seg0), 1: normal direction (seg0 ? seg 131 ) on indicates display on / off status 0: display on, 1: display off res indicates the initialization is in progress by resetb signal 0: c hip is active, 1: c hip is being reset. set page address sets the p age a ddress of display data ram from the microprocessor into the p age a ddress register. any ram data bit can be accessed when its p age a ddress and column address are specified. along with the column address, the p age a ddress defines the address of the display ram to write or read display data. changing the p age a ddress doesn't effect to the display status. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 1 p3 p2 p1 p0 p3 p2 p1 p0 specified page address 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 : : : : : : : : : : 1 1 0 1 1 3 1 1 1 0 1 4 1 1 1 1 1 5
132 seg / 128 com driver & controller for stn lcd preliminary spec. ver. 0. 1 S6B0728 32 set column address sets the c olumn a ddress of display ram from the microprocessor into the c olumn a ddress register. along with the c olumn a ddress, the c olumn a ddress defines the address of the display ram to write or read display data. when the microprocessor reads or writes display data to or from display ram, c olumn a ddresses are automatically incremented. set column address msb rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 y7 y6 y5 y4 set column address lsb rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 y3 y2 y1 y0 y7 y6 y5 y4 y3 y2 y1 y0 selected column address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 2 : : : : : : : : : : : : : : : : : : : : : : : : : : : 1 0 0 0 0 0 0 1 129 1 0 0 0 0 0 1 0 130 1 0 0 0 0 0 1 1 131 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 : : : : : : : : : : : : : : : : : : : : : : : : 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 not accessible column
S6B0728 preliminary spec. ver. 0 . 1 132 seg / 1 28 com driver & controller for stn lcd 33 set modify-read this instruction stops the automatic increment of the column address by the read display data instruction, but the column address is still increased by the write display data instruction. and it reduces the load of microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. this mode is canceled by the reset modify-read instruction. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 0 0 reset modify-read this instruction cancels the modify-read mode, and makes the column address return to its initial value just before the set modify-read instruction is started. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 1 1 1 0 set modify- r ead reset modify- r ead set page address data p rocess no y es change c omplete ? set column address (n) dummy read data r ead data w rite return c olumn a ddress (n) figure 23 . sequence for cursor display
132 seg / 128 com driver & controller for stn lcd preliminary spec. ver. 0. 1 S6B0728 34 display on / off turns the display on or off rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 1 1 d d = 1: display on d = 0: display off set initial display line register sets the line address of display ram to determine the initial display line using 2-byte instruction. the ram display data is displayed at the top row (com0) of lcd panel. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 0 0 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 s6 s5 s4 s3 s2 s1 s0 s6 s5 s4 s3 s2 s1 s0 selected line address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : : : : : : : : : : : : : : : : : 1 1 1 1 1 1 0 126 1 1 1 1 1 1 1 127 2 nd i nstruction (2- b yte i nstruction for r egister s etting) setting i nitial d isplay l ine e nd 1 st i nstruction (2- b yte i nstruction for m ode s etting) setting i nitial d isplay l ine s tart figure 24 . the sequence for setting the initial display line
S6B0728 preliminary spec. ver. 0 . 1 132 seg / 1 28 com driver & controller for stn lcd 35 set initial com0 register sets the initial row (com) of the lcd panel using the 2-byte instruction. by using this instruction, it is possible to realize the window moving without the change of display data. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 0 1 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 c6 c5 c4 c3 c2 c1 c0 c6 c5 c4 c3 c2 c1 c0 initial com0 0 0 0 0 0 0 0 com0 0 0 0 0 0 0 1 com1 0 0 0 0 0 1 0 com2 : : : : : : : : : : : : : : : : : : : : : : 1 1 1 1 1 0 1 com 125 1 1 1 1 1 1 0 com 126 1 1 1 1 1 1 1 com 127 setting i nitial com0 e nd 2 nd i nstruction ( i nitial com0 s etting) 1 st i nstruction ( m ode s etting) setting i nitial com0 s tart figure 25 . sequence for setting the initial com0
132 seg / 128 com driver & controller for stn lcd preliminary spec. ver. 0. 1 S6B0728 36 set partial display duty ratio sets the duty ratio within range of 16 to 1 28 to realize partial display by using the 2-byte instruction. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 1 0 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 d 7 d6 d5 d4 d3 d2 d1 d0 partial duty ratio 0 0 0 1 0 0 0 0 1/1 6 0 0 0 1 0 0 0 1 1/ 17 : : : : : : : : : : : : : : : : : : 0 1 1 1 1 1 1 1 1/ 127 1 0 0 0 0 0 0 0 1/1 28 other combinations no operation 2 nd i nstruction ( p artial d isplay d uty s etting) setting p artial d isplay e nd 1 st i nstruction ( m ode s etting) setting p artial d isplay s tart figure 26 . sequence for setting partial display
S6B0728 preliminary spec. ver. 0 . 1 132 seg / 1 28 com driver & controller for stn lcd 37 set n-line inversion register sets the inverted line number within range of 2 to 32 to improve the display quality by controlling the phase of the internal lcd ac signal (m) by using the 2-byte instruction. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 1 1 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 n4 n3 n2 n1 n0 n4 n3 n2 n1 n0 selected n-line inversion 0 0 0 0 0 0-line inversion (frame inversion) 0 0 0 0 1 2 -line inversion 0 0 0 1 0 3 -line inversion 0 0 0 1 1 4 -line inversion : : : : : : 1 1 1 0 1 30-line inversion 1 1 1 1 0 31-line inversion 1 1 1 1 1 32-line inversion 2 nd i nstruction ( n - l ine i nversion s etting) setting n - l ine i nversion e nd 1 st i nstruction ( m ode s etting) setting n - l ine i nversion s tart figure 27 . sequence for setting partial display release n-line inversion returns to the frame inversion condition from the n-line inversion condition. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 1 0 0
132 seg / 128 com driver & controller for stn lcd preliminary spec. ver. 0. 1 S6B0728 38 reverse display on / off reverses the display status on lcd panel without rewriting the contents of the display data ram. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 1 1 rev rev ram bit data = ? 1 ? ram bit data = ? 0 ? 0 (normal) lcd pixel is illuminated lcd pixel is not illuminated 1 (reverse) lcd pixel is not illuminated lcd pixel is illuminated entire display on / off forces the whole lcd points to be turned on regardless of the contents of the display data ram. at this time, the contents of the display data ram are held. this instruction has priority over the reverse d isplay on / off instruction. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 1 0 eon eon ram bit data = ? 1 ? ram bit data = ? 0 ? 0 (normal) lcd pixel is illuminated lcd pixel is not illuminated 1 (entire) lcd pixel is illuminated lcd pixel is illuminated power control selects one of eight power circuit functions by using 3-bit register. an external power supply and part of internal power supply functions can be used simultaneously. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 0 1 vc vr vf vc vr vf status of internal power supply circuits 0 1 internal voltage converter circuit is off internal voltage converter circuit is on 0 1 internal voltage regulator circuit is off internal voltage regulator circuit is on 0 1 internal voltage follower circuit is off internal voltage follower circuit is on
S6B0728 preliminary spec. ver. 0 . 1 132 seg / 1 28 com driver & controller for stn lcd 39 select dc/dc step-up selects one of 5 dc/dc step-up to reduce the power consumption by this instruction. it is very useful to realize the partial display function. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 1 0 0 dc2 dc1 dc0 dc1 dc0 dc0 selected dc-dc converter circuit 0 0 0 3 times boosting circuit 0 0 1 4 times boosting circuit 0 1 0 5 times boosting circuit 0 1 1 6 times boosting circuit 1 0 0 7 times boosting circuit regulator resistor select selects resistance ratio of the internal resistor used in the internal voltage regulator. see voltage regulator section in power supply circuit. refer to the table 15. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 0 0 r2 r1 r0 r2 r1 r0 [rb / ra] ratio 0 0 0 small 0 0 1 : : : : : 1 1 0 : 1 1 1 large
132 seg / 128 com driver & controller for stn lcd preliminary spec. ver. 0. 1 S6B0728 40 set electronic volume register consists of 2-byte instruction. the 1 st instruction sets electronic volume mode, the 2 nd one updates the contents of electronic volume register. after second instruction, electronic volume mode is released. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 0 0 0 0 1 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 ev5 ev4 ev3 ev2 ev1 ev0 ev5 ev4 ev3 ev2 ev1 ev0 reference voltage ( a ) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63 2 nd i nstruction for r egister s etting setting e lectronic v olume e nd 1 st i nstruction for m ode s etting setting e lectronic v olume s tart figure 28 . sequence for setting the electronic volume
S6B0728 preliminary spec. ver. 0 . 1 132 seg / 1 28 com driver & controller for stn lcd 41 select lcd bias selects lcd bias ratio of the voltage required for driving the lcd. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 1 0 b2 b1 b0 b2 b1 b0 selected lcd bias 0 0 0 1/5 0 0 1 1/6 0 1 0 1/7 0 1 1 1/8 1 0 0 1/9 1 0 1 1/10 1 1 0 1/11 1 1 1 1/1 2 shl select com output scanning direction is selected by this instruction which determines the lcd driver output status. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 0 0 shl shl = 0: normal direction (com0 ? com 127 ) shl = 1: reverse direction (com 127 ? com0) adc select changes the relationship between ram column address and segment driver. the direction of segment driver output pins can be reversed by software. this makes ic layout flexible in lcd module assembly. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 0 0 adc adc = 0: normal direction (seg0 ? seg 131 ) adc = 1: reverse direction (seg 131 ? seg0)
132 seg / 128 com driver & controller for stn lcd preliminary spec. ver. 0. 1 S6B0728 42 oscillator on start this instruction enables the built-in oscillator circuit. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 0 1 1 reset this instruction resets initial display line, column address, page address, and common output status select to their initial status, but dose not affect the contents of display data ram. this instruction cannot initialize the lcd power supply that is initialized by the resetb pin. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 1 0
S6B0728 preliminary spec. ver. 0 . 1 132 seg / 1 28 com driver & controller for stn lcd 43 power save the S6B0728 enters the p ower s ave status to reduce the power consumption to the static power consumption value and returns to the normal operation status by the following instructions. set power save mode rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 0 0 1 release power save mode rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 0 1 the internal status during power save mode are as follows : - oscillator c ircuit : off - lcd p ower s upply c ircuit : off - all com / seg o utput l evel : vss - consumption current < 2 m a nop no n- operation rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 1 1 test instruction this instruction is for testing ic. please do not use it. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 1
132 seg / 128 com driver & controller for stn lcd preliminary spec. ver. 0. 1 S6B0728 44 referential instruction setup flow: initializing with the built-in power supply circuits user s ystem s etup by e xternal p ins start of i nitialization power o n (vdd-vss) k eeping the resetb p in = "l" waiting for s tabilizing the p ower resetb pin = "h" user a pplication s etup by i nternal i nstructions [display duty select] [adc select] [shl select] [com0 register select] user lcd power s etup by i nternal i nstructions [oscillator on] [dc-dc step-up register select] [regulator resistor select] [electronic volume register select] [lcd bias register select] [power control] waiting for s tabilizing the lcd power levels end of i nitialization figure 29 . initializing w ith t he built- i n power supply circuits
S6B0728 preliminary spec. ver. 0 . 1 132 seg / 1 28 com driver & controller for stn lcd 45 referential instruction setup flow: initializing without the built-in power supply circuits user system setup by external pins start of initialization power on (vdd-vss) keeping the resetb pin = "l" waiting for stabilizing the power set power save user application setup by internal instructions [display duty select] [adc select] [shl select] [com0 register select] user lcd power setup by internal instructions [oscillator on] regulator or follower register select [power control] waiting for stabilizing the lcd power levels end of initialization resetb pin = "h" release power save figure 30 . initializing without the built-in power supply circuits
132 seg / 128 com driver & controller for stn lcd preliminary spec. ver. 0. 1 S6B0728 46 referential instruction setup flow: data displaying end of i nitialization write display data by i nstruction [display data write] turn display on/off i nstruction [display on/off] end of d ata d isplay display data ram addressing by i nstruction [initial display line] [set page address] [set column address] figure 31 . data displaying r eferential instruction setup flow: power off optional status power off (vdd-vss) end of p ower o ff set power save by i nstruction figure 32 . power off
S6B0728 preliminary spec. ver. 0 . 1 132 seg / 1 28 com driver & controller for stn lcd 47 referential instruction setup flow: partial duty changing start of partial changing set display off by internal instruction [display on / off] set partial duty by internal instructions [partial display duty ratio select] [initial display line register] [com0 register select] user lcd power setup by internal instructions [dc-dc step-up register select] [regulator resistor select] [electronic volume register select] [lcd bias register select] [power control] waiting for stabilizing the lcd power levels end of partial changing release power save set standby mode by internal instruction [power save mode] write display data & display on by internal instruction [display data write] [display on / off] waiting for discharging the lcd power levels figure 33 . partial duty changing
132 seg / 128 com driver & controller for stn lcd preliminary spec. ver. 0. 1 S6B0728 48 specifications absolute maximum ratings table 18 . absolute maximum ratings (vss = 0v) parameter symbol rating unit v dd - 0.3 ~ + 7.0 v v0, vout + 0.3 ~ + 20.0 v supply voltage range v1, v2, v3, v4 + 0.3 ~ v0 v external reference voltage vext +0.3 ~ v dd input voltage range v in - 0.3 ~ v dd + 0.3 v operating temperature range t opr - 40 ~ + 85 c storage temperature range t str - 55 ~ + 125 c notes : 1. vdd, v0, vout, v1 to v4, vext and vci are based on vss = 0v. 2. voltage vout 3 v0 3 v1 3 v2 3 v3 3 v4 3 vss must always be satisfied. 3. if supply voltage exceeds its absolute maximum range, this lsi may be damaged permanently. it is desirable to use this lsi under electrical characteristic conditions during general operation. otherwise, this lsi may malfunction or reduced lsi reliability may result.
S6B0728 preliminary spec. ver. 0 . 1 132 seg / 1 28 com driver & controller for stn lcd 49 dc characteristics table 19 . dc characteristics (v ss = 0v, v dd = 2.4 to 3.6 v, ta = -40~85 c) item symbol condition min. typ. max. unit pin used operating voltage (1) v dd 2.4 - 3.6 v v dd *1 operating voltage (2) v0 4.0 - 17.0 v v0, *2 high v ih 0.8v dd - v dd input voltage low v il v ss - 0.2v dd v *3 high v oh i oh = -0.5ma 0.8v dd - v dd output voltage low v ol i ol = 0.5ma v ss - 0.2v dd v *4 input leakage current i il v in = v dd or v ss - 1.0 - + 1.0 m a *3 output leakage current i oz v in = v dd or v ss - 3.0 - + 3.0 m a *5 lcd driver on resistance r on ta = 25 c, v0 = 8v - 2.0 3.0 k w segn comn *6 frame frequency f fr ta = 25 c 70 85 100 hz *7 fr table 20 . dc characteristi cs item symbol condition min. typ. max. unit pin used voltage converter circuit output voltage vout 3/ 4/ 5/ 6 / 7/ voltage conversion (no-load ) 95 99 - % vout voltage regulator circuit operating voltage vout 6.0 - 19.0 v vout voltage follower circuit operating voltage v0 4.0 - 17.0 v v0 *8 reference voltage v ref ta = 25 c 1.94 0 2.00 0 2.06 0 v *9
132 seg / 128 com driver & controller for stn lcd preliminary spec. ver. 0. 1 S6B0728 50 dynamic current consumption (1) when an external power supply is used. table 21 . display off (vdd = 3.0v, ta = 25 c) item symbol condition min. typ. max. unit pin used v0 - vss = 1 0 .0v, duty = 1/6 4 tbd dynamic current consumption (1) idd 1 v0 - vss = 1 5 .0v, duty = 1/1 28 tbd m a *10 table 22 . checker pattern (vdd = 3.0v, ta = 25 c) item symbol condition min. typ. max. unit pin used v0 - vss = 1 0 .0v, duty = 1/6 4 tbd dynamic current consumption (1) idd 1 v0 - vss = 1 5 .0v, duty = 1/1 28 tbd m a *10 dynamic current consumption (2) when the internal power supply is on table 23 . display off (vdd = 3.0v, ta = 25 c) item symbol condition min. typ. max. unit pin used v0 - vss = 1 0 .0v, x 4 boosting, duty = 1/6 4, bias = 1/9 - - tbd m a *10 dynamic current consumption (2) idd2 v0 - vss = 15.0v, x6 boosting, duty = 1/1 28, bias = 1/12 - - tbd m a *10 table 24 . check pattern (vdd = 3.0v, ta = 25 c) item symbol condition min. typ. max. unit pin used v0 - vss = 1 0 .0v, x 4 boosting, duty = 1/6 4, bias = 1/9 - - tbd dynamic current consumption (2) idd2 v0 - vss = 15.0v, x6 boosting, duty = 1/1 28, bias = 1/12 - - tbd m a *10 dynamic current consumption during power save mode table 25 . power save mode (vdd = 3.0v, ta = 25 c) item symbol condition min. typ. max. unit pin used power save mode current idds during power save - - 2 m a
S6B0728 preliminary spec. ver. 0 . 1 132 seg / 1 28 com driver & controller for stn lcd 51 table 26 . the relationship between oscillation frequency and frame frequency duty ratio item f cl f osc 1/n on-chip oscillator circuit is used f fr x n f fr x 2 x n (f osc : oscillation frequency, f cl : display clock frequency, f fr : frame frequency, n = 16 to 1 28 ) [* remark solves] *1 . though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from the mpu. *2 . in case of external power supply is applied. *3 . cs1b, cs2, rs, db0 to db7, e_rd, rw_wr, resetb, c68, ps, intrs, ref , cl, m *4 . db0 to db7 , cl, m *5 . applies when the db0 to db7 pins are in high impedance. *6 . resistance value when -0.1[ma] is applied during the on status of the output pin segn or comn. ron [k w ] = d v[v] / 0.1[ma] ( d v : voltage change when -0.1[ma] is applied in the on status.) *7 . see table 26 for the relationship between oscillation frequency and frame frequency. *8 . the voltage regulator circuit adjusts v0 within the voltage follower operating voltage range. *9 . on-chip reference voltage source of the voltage regulator circuit to adjust v0. *10 . applies to the case where the on-chip oscillation circuit is used and no access is made from the mpu. the current consumption, when the built-in power supply circuit is on or off. the current flowing through voltage regulation resistors (rb and ra) is not included. it does not include the current of the lcd panel capacity, wiring capacity, etc.
132 seg / 128 com driver & controller for stn lcd preliminary spec. ver. 0. 1 S6B0728 52 ac characteristics read / write characteristics (8080-series mpu) t dh80 t od80 t ds80 t acc80 0.9v dd 0.1v dd t pwlw , t pwlr t cy80 t ah80 t as80 db0 to db7 ( write ) db0 to db7 ( read ) /rd, /wr cs1b rs t pwhw , t pwhr figure 34 . parallel interface (8080-series mpu) timing diagram table 27 . ac characteristics (8080-series p arallel m ode) (v dd = 2.4 ~ 3.6 v, ta = -40 ~ +85 c) item signal symbol condition min. max. unit address setup time address hold time rs t as80 t ah80 tbd tbd - - ns system cycle time t cy80 tbd - ns pulse width low for write pulse width high for write rw_wr (/wr) t pwlw t pwhw tbd tbd - - ns pulse width low for read pulse width high for read e_rd (/rd) t pwlr t pwhr tbd tbd - - ns data setup time data hold time t ds80 t dh80 tbd tbd - - ns read access time output disable time db0 to db7 t acc80 t od80 cl = 100 pf tbd tbd tbd tbd ns note: *1. the input signal rise time and fall time (tr, tf) is specified at 15 ns or less. (tr + tf) < (tcy80 - tpwlw - tpwhw ) for write, (tr + tf) < (tcy80 - tpwlr - tpwhr ) for read
S6B0728 preliminary spec. ver. 0 . 1 132 seg / 1 28 com driver & controller for stn lcd 53 read / write characteristics (6800-series microprocessor) t dh68 t od68 t ds68 t acc68 0.1v dd 0.9v dd t ewhw , t ewhr t cy68 t ah68 t as68 db0 to db7 ( write ) db0 to db7 ( read ) e cs1b rs, r/w t ewlw , t ewlr figure 35 . parallel interface (6800-series mpu) timing diagram table 28 . ac characteristics (6800-series p arallel m ode) (v dd = 2.4 ~ 3.6 v, ta = -40 ~ +85 c) item signal symbol condition min. max. unit address setup time address hold time rs rw t as68 t ah68 tbd tbd - - ns system cycle time t cy68 tbd - ns enable width high for write enable width low for write e_rd (e) t ewhw t ewlw tbd tbd - - ns enable width high for read enable width low for read e_rd (e) t ewhr t ewlr tbd tbd - - ns data setup time data hold time t ds68 t dh68 tbd tbd - - ns read access time output disable time db0 to db7 t acc68 t od68 c l = 100 pf - tbd tbd tbd ns note: *1. the input signal rise time and fall time (tr, tf) is specified at 15 ns or less. (tr + tf) < (tcy68 - tewhw - tewlw ) for write, (tr + tf) < (tcy68 - tewhr - tewlr ) for read
132 seg / 128 com driver & controller for stn lcd preliminary spec. ver. 0. 1 S6B0728 54 serial interface characteristics db7 ( sid ) db6 ( sclk ) rs cs1b (cs2 = 1 ) t dhs t dss t whs 0.9v dd 0.1v dd t wls t cys t ahs t ass t chs t css figure 36 . serial interface timing diagram table 29 . ac characteristics (serial mode) (v dd = 2.4 ~ 3.6 v, ta = -40 ~ +85 c) item signal symbol condition min. max. unit serial clock cycle sclk high pulse width sclk low pulse width db6 (sclk) ts cy ts hw ts lw tbd tbd tbd - - - ns address setup time address hold time rs t ass t ahs tbd tbd - - ns data setup time data hold time db7 (sid) t dss t dhs tbd tbd - - ns cs1b setup time cs1b hold time cs1b t css t chs tbd tbd - - ns note: *1. the input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
S6B0728 preliminary spec. ver. 0 . 1 132 seg / 1 28 com driver & controller for stn lcd 55 reset input timing resetb internal status t rw t r reset complete during reset figure 37 . reset input timing diagram table 30 . ac characteristics (reset mode) (v dd = 2.4 ~ 3.6 v, ta = -40 ~ +85 c) item signal symbol condition min. max. unit reset low pulse width resetb t rw 1000 - ns reset time - t r - 1000 ns
132 seg / 128 com driver & controller for stn lcd preliminary spec. ver. 0. 1 S6B0728 56 reference applications microprocessor interface db0 to db7 resetb v dd v dd rw e rs cs2 cs1b 6800-series mpu cs1b cs2 rs e_rd rw_wr db0 to db7 resetb c68 ps s6b 07 28 figure 38 . in case of interfacing with 6800-series (ps = ? h ? , c68 = ? h ? ) resetb v dd v ss /wr /rd rs cs2 cs1b 8080-series mpu cs1b cs2 rs e_rd rw_wr db0 to db7 resetb c68 ps s6b 07 28 figure 39 . in case of interfacing with 8080-series (ps = ? h ? , c68 = ? l ? ) open resetb vss vdd sclk sid rs cs2 cs1b mpu cs1b cs2 rs db7(sid) db6(sclk) resetb db0 to db5 c68 ps s6b 07 28 figure 40 . in case of 4-pin spi interface (ps = ? l ? , c68 = ? h ? ) open resetb vss vss sclk sid rs cs2 cs1b mpu cs1b cs2 rs db7(sid) db6(sclk) resetb db0 to db5 c68 ps s6b 07 28 figure 41 . in case of 3-pin spi interface (ps = ? l ? , c68 = ? l ? )
S6B0728 preliminary spec. ver. 0 . 1 132 seg / 1 28 com driver & controller for stn lcd 57 connections between S6B0728 and lcd panel (1/1 28 duty configurations) com 127 - com 64 seg 131 seg 130 ? seg1 seg0 s6b 07 28 (bottom view) 128 1 32 pixels com 63 - com 0 com 127 - com 64 seg 0 seg 1 ? seg1 30 seg131 s6b0 7 28 ( top view) 128 1 32 pixels com 63 - com 0 figure 42 . shl = 0, adc = 0 figure 43 . shl = 0, adc = 1 com 127 - com 64 seg 131 seg 130 ? seg1 seg0 s6b 07 28 (bottom view) 128 1 32 pixels com 63 - com 0 com 127 - com 64 seg 0 seg 1 ? seg1 30 seg131 s6b 7 28 ( top view) 128 1 32 pixels com 63 - com 0 figure 44 . shl = 1, adc = 0 figure 45 . shl = 1, adc = 1

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